FIG. 1 is a schematic cross-sectional view illustrating a memory cell of a conventional programmable dual-poly nonvolatile memory. The memory cell comprises a floating-gate transistor. As shown in FIG. 1, this floating-gate transistor comprises two stacked and separated gates. The upper gate is a control gate 12, which is connected to a control line C. The lower gate is a floating gate 14. In addition, an n-type doped source region and an n-type doped drain region are constructed in a P-substrate. The n-type doped source region is connected to a source line S. The n-type doped drain region is connected to a drain line D.
For example, in case that the nonvolatile memory is in a programmed state, a high voltage (e.g. +16V) is provided by the drain line D, a ground voltage is provided by the source line S, and a control voltage (e.g. +25V) is provided by the control line C. Consequently, during the process of transmitting the electrons from the source line S to the drain line D through an n-channel region, the hot carriers (e.g. hot electrons) are attracted by the control voltage at the control gate 12 and injected into the floating gate 14. Under this circumstance, a great number of carriers are accumulated in the floating gate 14. Consequently, the programmed state may be considered as a first storage state (e.g. “0” state).
In case that the nonvolatile memory is in a non-programmed state, no carrier is injected into the floating gate 14, and thus the non-programmed state may be considered as a second storage state (e.g. “1” state).
In other words, the characteristic curve of the drain current (id) and the gate-source voltage (Vgs) (i.e. an id-Vgs characteristic curve) in the first storage state and the id-Vgs characteristic curve in the second storage state are distinguished. Consequently, the storage state of the floating-gate transistor may be realized according to the variation of the id-Vgs characteristic curve.
However, since the floating gate 14 and the control gate 12 of the dual-poly nonvolatile memory should be separately produced, the process of fabricating the dual-poly nonvolatile memory needs more steps and is incompatible with the standard CMOS manufacturing process.
Moreover, U.S. Pat. No. 6,678,190 discloses a programmable single-poly nonvolatile memory. FIG. 2A is a schematic cross-sectional view illustrating a memory cell of a conventional programmable single-poly nonvolatile memory disclosed in U.S. Pat. No. 6,678,190. FIG. 2B is a schematic top view illustrating the memory cell of the conventional programmable single-poly nonvolatile memory of FIG. 2A. FIG. 2C is a schematic circuit diagram illustrating the memory cell of the conventional programmable single-poly nonvolatile memory of FIG. 2A.
Please refer to FIGS. 2A-2C. The memory cell of the conventional programmable single-poly nonvolatile memory comprises two serially-connected p-type metal-oxide semiconductor (PMOS) transistors. The first PMOS transistor is used as a select transistor, and a select gate 24 of the first PMOS transistor is connected to a select gate voltage VSG. A p-type doped source region 21 is connected to a source line voltage VSL. Moreover, a p-type doped drain region 22 may be considered as a combination of a p-type doped drain region of the first PMOS transistor and a first p-type doped region of the second PMOS transistor. A floating gate 26 is disposed over the second PMOS transistor. A second p-type doped region 23 of the second PMOS transistor is connected to a bit line voltage VBL. Moreover, these PMOS transistors are constructed in an N-well region (NW). The N-well region is connected to an N-well voltage VNW.
By properly controlling the select gate voltage VSG, the source line voltage VSL, the bit line voltage VBL and the N-well voltage VNW, the conventional programmable single-poly nonvolatile memory may be operated in a programmed state or a read state.
Since the two PMOS transistors of the memory cell of the conventional programmable single-poly nonvolatile memory have respective gates 24 and 26, the process of fabricating the conventional programmable single-poly nonvolatile memory is compatible with the standard CMOS manufacturing process.
As described in FIGS. 1 and 2, the memory cell of the nonvolatile memory is only programmable. The electrical property of the nonvolatile memory is only utilized to inject a great number of hot carriers to the floating gate. However, the electrical property fails to be utilized to remove the carriers from the floating gate. That is, for achieving the data-erasing function, the carriers stored in the floating gate may be removed from the floating gate by exposing ultraviolet (UV) light to the nonvolatile memory. Consequently, the memory cell of this nonvolatile memory is referred as a one time programming (OTP) cell.
Therefore, for improving the memory cells of the programmable single-poly nonvolatile memory, there is a need of providing an array structure of multi-times programming (MTP) cells, one time programming (OTP) cells and/or mask read only memory (ROM) cells.